MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
Features
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application;
- SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 40um * 270um with DUP stagger bonding pads;
- Work IO voltage: 1.2V/1.5V/1.8V;
- Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066;
- Suitable for 7, 8, 9 and 10 layers application ;
View SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application full description to...
- see the entire SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application datasheet
- get in contact with SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application Supplier