VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic low voltage 1P7M Salicide 1.2/1.5V process. This library is fully compliant with the EIA/JEDEC standard, JESD8-6, HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS published in August 1995 .
The HSTL provides MOS push-pull interface designs and is especially optimized for major memory applications. It is intended to improve operation in situations where busses must be isolated from relatively large stubs. Comparing to the LVTTL solution, HSTL has the advantages of lower voltage swing, lower power dissipation and higher immunity to generated noise because of the differential receiver.
There are two classes of output specifications for HSTL, class I and class II, which are distinguished by drive requirements and application. Class I is basically applied for point-to-point configuration, such as network applications, and Class II is mostly applied for DDR/DDRII SDRAM signaling.
- SMIC 0.13um Logic High Speed 1P7M Salicide 1.2V/1.5V process
- 1.2V core and 1.5V External interface
- Meet HSTL DC input levels and HSTL AC output levels
- On Die Terminate Resistor
- Pad pitch: 100um (which is designed for area IO)
- Cell height: 200um
- Suitable for five, six, seven metal layers physical design
- Fully compliant with the EIA/JEDEC standard, JESD8-6
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist