SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
The HSTL provides MOS push-pull interface designs and is especially optimized for major memory applications. It is intended to improve operation in situations where busses must be isolated from relatively large stubs. Comparing to the LVTTL solution, HSTL has the advantages of lower voltage swing, lower power dissipation and higher immunity to generated noise because of the differential receiver.
There are two classes of output specifications for HSTL, class I and class II, which are distinguished by drive requirements and application. Class I is basically applied for point-to-point configuration, such as network applications, and Class II is mostly applied for DDR/DDRII SDRAM signaling.
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