The D16450 is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450. It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported information status includes the type and a condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16450 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. Our proprietary solution has also a complete MODEM control capability and a processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communication link.
The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
The core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Our solution is also dedicated for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to the D16450 universal interface, both, core implementation and verification, are very simple. They could be done by only eliminating a number of clock trees in the complete system.
The D16450 includes a fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.
Our trustworthy solution is a technology independent design, that can be implemented in a variety of process technologies.
- Software compatible with 16450 UART
- Configuration capability
- Separate configurable BAUD clock line
- Majority Voting Logic
- Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts
- False start bit detection
- 16 bit programmable baud generator
- Independent receiver clock input
- MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
- Fully programmable serial-interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1-, 1,5-, or 2-stop bit generation
- Internal baud generator
- Complete status reporting capabilities
- Line break generation and detection. Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
- Full prioritized interrupt system controls
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design and no internal tri-states
- Serial Data communications applications
- Modem interface
- Embedded microprocessor boards
Block Diagram of the Soft core of the UART functionally of the TL16C450