CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random access memory (SDRAM). The design consists of an AXI controller, read and write data buffers, and a single instantiation of CoreSDR, which contains a generic CPU interface.
- High performance, SDR controller for standard SDRAM chips and dual in-line memory (DIMMs)
- Accesses the AXI slave interface through the SmartFusion®2 REVFIC64 fabric interface
- Supports 8,16, and 32-bit memory
- Supports up to 1,024 MB of memory
- Bank management logic monitors status of up to 8 SDRAM banks
- Fully synchronous, buffered register interface