The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA. It serves as a direct replacement for an external LVDS receiver IC and takes advantage of the fast LVDS I/O solutions provided by modern FPGA devices.
The interface supports both single-mode and double-mode operation in which 4 x LVDS data lanes or 8 x LVDS data lanes may be connected to the IP Core. In the standard configuration, the camera input clock (TXCLKOUT_P/N) is assumed to be set to a frequency of 74.25 MHz. This permits operation at HD1080p30 resolution in single-mode (1x16-bit pixels per clock) or HD1080p60 operation in double-mode (2x16-bit pixels per clock).
The LVDS data lanes are deserialized using the high-speed SERDES input resources of the FPGA.. The resulting parallel data are then aligned and decoded to provide a standard SMPTE 274M output video stream. SMPTE data changes on the rising-clock edge of the SMPTE_TCLK (cam_clk) signal.
Other flags are also provided to indicate the presence of active video, the start of an active frame and the start of an active line. In addition, there is a stream locked flag that indicates the bit alignment has succeeded and a valid SMPTE stream has been found.
- Compatible with all Sony® FCB-EV Series LVDS video cameras
- Support for HD1080p60 (double-mode)
- Support for HD1080p30 (single-mode)
- Choice of 8 or 4 x LVDS data lanes
- Generates a standard SMPTE 274M output video stream
- Simple connectivity to the Sony® FCB-EV series HD-cameras
- Easily adaptable for other LVDS cameras
- Replacement for the Thine® THC63LVD series LVDS receiver ICs
- Replacement for the Rohm® BU90R series LVDS receiver ICs
Block Diagram of the Sony Camera LVDS Interface IP Core