Spatial image transformation accelerator
The Spatial image transformation core is packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the module allowing the designer to adjust for different image processing pipelines.
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Block Diagram of the Spatial image transformation accelerator IP Core

image processing IP
- Image Signal Processing (ISP) RTL IP for IR/Mono/RGB Bayer/RGB-IR/PDAF/HDR/Fish Eye/3A Sensors Image Process to Human/Machine Vision
- UHD Image Signal Processing (ISP) Pipeline
- ISP (Image Signal Processor) with the minimum functions required for image processing system
- 8-13M pixel sensor support High Quality Image Signal Processing (ISP) IP
- FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x000D_
- Fast and efficient two-dimensional FFT core for image processing applications