Our SPDIF (Sony/Philips Digital Interface) Controller IP is a core that implements the Sony/Philips Digital Interface (IEC 60958), which is an unidirectional and self-clocking interface for connecting digital audio equipment by using linear and non-linear PCM coded audio samples. The non-linear usage occurs with pass-through supported.
The IP is architected to quickly and easily integrate into any system-on-chip (SoC) thanks to the adherence to interface standards such as AMBA 2 APB and provides a convenient, cost-effective solution offering advanced configurability. High performance is yet another characteristic feature of the compact architecture offered by the Cadence Sony/Philips Digital Interface Controller IP, affecting the silicon size and increasing power saving.
- Compliant with AMBA 2 On-Chip Bus specification, AMBA APB supported
- Receiver and transmitter modes available
- Data mode capabilities such as: sample rate 3kHz-192kHz and 20/24 bit per sample
- Synchronization hold in the under-run condition, clock recovery from the SPDIF data stream
- Sample rate detection from the received data stream
- Integrated AMBA APB slave wrapper to interface with the APB controller
- DMA master handshake interfacing supported
- Event stimulated internal interrupt request generation with masking capability
- Configurable size of external FIFO (64 words default), 64 to 512 word depth of the FIFO memo
- Clean, readable, synthesizable Verilog HDL
- Cadence Encounter® RTL
- Compiler synthesis scripts
- Documentation – integration and user guide, release notes
- Sample verification testbench