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SPI-4 Phase 2 Interface Solutions
The Xilinx SPI-4 Phase 2 core provides a fully compliant Packet-Over-SONET/SDH (POS) solution, which can be quickly integrated into networking systems.
Through user-configurable options, the Xilinx SPI-4.2 core provides ultimate flexibility while seamlessly interoperating with industry leading ASSPs to maximize the data transfer bandwidth. The Xilinx SPI-4.2 core is fully compliant with the OIF's System Packet Interface Level 4 (SPI-4) Phase 2 standard, as well as the SATURN® Development Group's POS-PHY Level 4 (PL4) interface specification.
Through user-configurable options, the Xilinx SPI-4.2 core provides ultimate flexibility while seamlessly interoperating with industry leading ASSPs to maximize the data transfer bandwidth. The Xilinx SPI-4.2 core is fully compliant with the OIF's System Packet Interface Level 4 (SPI-4) Phase 2 standard, as well as the SATURN® Development Group's POS-PHY Level 4 (PL4) interface specification.
Features
- Up to 700 MHz DDR on SPI-4.2 interface supporting 1.2 Gbps pin pair total bandwidth
- Supports Static and Dynamic Phase Alignment utilizing ChipSync™ technology
- Bandwidth optimized source core achieves optimal bus throughput without additional FPGA resources
- Flexible clocking options utilizing DCM, PMCD, global, and regional clocking resources
- SelectIO™ technology supports flexible pin assignment
- Configurable 64-bit or 128-bit user interface, both supporting full bandwidth capabilities
- Supports unsegmented burst sizes up to 16K
- Optional continuous DPA window monitoring
- Optional advanced DPA diagnostics
- Multiple core support: more than 4 cores can be implemented in a single device
- Sink and Source cores independently configured through Xilinx CORE Generator™ system for easy customization
- Supports 1 to 256 addressable channels with fully configurable SPI-4.2 calendar interface
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Interface and Interconnect
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core