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LTE NB-IOT (NB1) power optimized transceiver for cellular IoT
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SPI Flash Memory Controller
SPI flash memory controller allows flexible, fast and high performance implementation of an AHB subsystem having SPI flash memories and offloading AHB master from direct control of SPI flash memories and executes SPI data operations. It supports up to 16 flash memory devices of any memory size organized in up to 4 memory clusters. AHB master configures SPI controller, provides necessary data (in the case of memory write operation) or read data (in the case of memory read operation) and starts SPI controller. SPI controller can decode and execute SPI flash memory instructions controlling directly SPI flash memories and offload AHB master from this task.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
Features
- SPI flash memory controller with AHB slave interface
- Decodes and executes SPI flash memory instructions issued by AHB master
- Provides accurate control signals timing on SPI flash memory interface
- Allows efficient data transfers (read/write) between AHB master and SPI flash memories
- Set of configuration registers to control efficient data transfer between AHB master and SPI flash memories and facilitate software control of SPI controller
- Provides the information about the status and outcome of data transfer to AHB master by interrupt mechanism and status register
- Supports hierarchical organization of SPI flash memories:
- up to 4 SPI flash memory clusters
- up to 4 SPI flash memories in each cluster
- Data transfers can be executed in parallel at SPI memory cluster level providing additional offload level for AHB master
- Dual port Tx/Rx FIFO for each flash memory cluster Interrupts mechanism
- Supports different SPI memory serial clock speeds (up to 4 different SPI clocks can be selected by software)
- Supports Spansion S25FL-P and compatible flash memories in all modes of operation
- Easily customized by a number of design parameters
- Two independent clock domains: AHB and SPI
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