SPI Flash Memory Controller
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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flash IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- LDPC Encoder/Decoder (LDPC)
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 3.2 NAND Flash Controller
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- xSPI Flash Memory Controller