SPI Flash Memory Controller

SPI flash memory controller allows flexible, fast and high performance implementation of an AHB subsystem having SPI flash memories and offloading AHB master from direct control of SPI flash memories and executes SPI data operations. It supports up to 16 flash memory devices of any memory size organized in up to 4 memory clusters. AHB master configures SPI controller, provides necessary data (in the case of memory write operation) or read data (in the case of memory read operation) and starts SPI controller. SPI controller can decode and execute SPI flash memory instructions controlling directly SPI flash memories and offload AHB master from this task.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.

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