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SPI -Master-APB
Caliber's Serial Peripheral Interface (SPI) IP Core performs Serial data communication between Master and Slave SPI devices with a full-duplex, synchronous, four-wire, serial bus interface. SPI initiates the data frame from Master to One/Multiple Slave devices.
SPI IP core application interface is FIFO/CSR/AXI4-Lite/APB/Avalon-MM Interface and client interface is standard MOSI, MISO, CS, SCLK line interface.
SPI IP core application interface is FIFO/CSR/AXI4-Lite/APB/Avalon-MM Interface and client interface is standard MOSI, MISO, CS, SCLK line interface.
Features
- Run time configurable 8,16,32 bits data transfer mode
- Supports at system clock frequency 32,45,50,100,150(MHz)
- Supports Byte and Burst transfer/receive mode of operation
- Programmable master mode clock frequencies
- Interrupt generation for Read/Write success with masking
- Transmit and receive FIFO depths is user configurable
- Internal 16 bit programmable baud rate generator
- Flexible user control full duplex mode operation
- Programmable Polarity and Phase
- Built in Debug Logic feature to simplify the debugging process
- Built in Latency and Throughput measurement of IO interface
- Provision to validate the SPI IP core features using loop back mode testing
- Fully synthesizable synchronous design with positive edge clocking
Deliverables
- SPI Master IP Core Interface is available in Verilog - HDL source code and Netlist on target device/technology
- User Manual for SPI IP Core Interface and SPI IP Core Verification user manual
- Tools specific scripts for simulation and Synthesis
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SPI
- Octal SPI Flash Controller and PHY
- Quad SPI Controller with Execute in Place AHB/APB/AXI
- AHB Octal SPI Controller with Execute in Place (70114)
- Flash SPI controller master/slave
- Quad-SPI FLASH Controller AHB
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA