The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can be programmed to run either in standard SPI mode where bidirectional one byte transactions are implemented, or in extended SPI mode where frame transactions are implemented as an SPI EEPROM Controller. The MSPIM IP controls all SPI-bus specific sequences, protocol and timing. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
- Single-chip synchronous SPI Master IP in FPGA
- Designed to be included in high-speed and high-performance applications
- Direct Connection to CPU register set
- High frequency rate
- Two run-time mode : Standard SPI mode and Extended SPI mode as SPI EEPROM controller
- Synchronised on system clock
- Serial clock programmable with polarity and phase
- Serial clock period can be at least 6 system clock period
- FPGA speed grade operating frequency dependant
- Available in VHDL source code format for ease of customization
- DO254 documentation available
- Can be customized by Logic Design Solutions
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet
- Reference Guide
- User’s guide
- Simulation, Synthesis and Place and Route procedures.
- Constraint File