SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The DB-SPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.
View SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) full description to...
- see the entire SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) datasheet
- get in contact with SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) Supplier
SPI IP
- Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
- AHB Quad SPI Controller with Execute in Place (70115)
- High Speed SPI AHB IP Core- Serial Peripheral Interface
- AHB Octal SPI Controller with Execute in Place (70114)
- Flash SPI controller master/slave
- SPI Flash Memory Controller