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SPI Slave Serial Interface Controller
Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device.
The controller uses a series of registers as a data structure to communicate between Master and Slave.
The controller uses a series of registers as a data structure to communicate between Master and Slave.
Features
- SPI compliant
- Simple SPI programming
- Configurable number of config registers
- Configurable number of status registers
- Configurable clock polarity (CPOL)
- Configurable clock phase (CPHA)
Benefits
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation testbench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
Block Diagram of the SPI Slave Serial Interface Controller IP Core
View SPI Slave Serial Interface Controller full description to...
- see the entire SPI Slave Serial Interface Controller datasheet
- get in contact with SPI Slave Serial Interface Controller Supplier
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