The SPI to AXI4 Controller Bridge IP core enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx Zynq-7000 AP SoC and FPGAs through the Serial Peripheral Interface (SPI) bus. The SPI is a full-duplex synchronous four-wire serial interface between a single bus master, and one or more bus slave devices.
The SPI to AXI4 Controller Bridge IP core works as a SPI Slave controller and a 32-bit master controller on the ARM AMBA Advanced eXtensible Interface (AXI4) on-chip bus. It accepts and decodes a number of command SPI telegrams and allows the MCU to control peripherals implemented in the Zynq-7000 SoC or FPGA, or communicate with on-chip processors. Implemented bursting mechanism allows for large (2Kbytes) data transfers between on-chip and off-chip memories controlled by Xilinx programmable devices.
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- Supports Xilinx® ZynqTM-7000 AP SoC and all Xilinx FPGAs
- Bridge controller between the serial SPI bus and the parallel AXI4 bus
- Works as a Slave controller on the SPI bus
- ARM® AMBA® AXI4 compliant master controller
- Supports SPI telegrams of different lenghts: single transfers and burst transfer (up to 2KB, back-to-back)
- Supports SCLK frequency of up to 1/4 of the system clock (AXI4 clock)
- Supports all SPI clock polarity (CPOL) and phase (CPHA) combinations
- Fully embedded into Xilinx XPS and the EDK
- Easy control Xilinx FPGA and Zynq-7000 SoC implemented co-processors by virtually any microcontroller (MCU)