ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
SPI to AXI4 Controller Bridge
The SPI to AXI4 Controller Bridge IP core works as a SPI Slave controller and a 32-bit master controller on the ARM AMBA Advanced eXtensible Interface (AXI4) on-chip bus. It accepts and decodes a number of command SPI telegrams and allows the MCU to control peripherals implemented in the Zynq-7000 SoC or FPGA, or communicate with on-chip processors. Implemented bursting mechanism allows for large (2Kbytes) data transfers between on-chip and off-chip memories controlled by Xilinx programmable devices.
View SPI to AXI4 Controller Bridge full description to...
- see the entire SPI to AXI4 Controller Bridge datasheet
- get in contact with SPI to AXI4 Controller Bridge Supplier