Precise-ITC offers a dynamically reconfigurable SDH/OTN Nx10G multi-lane multi-protocol transponder/mapper FPGA solution for 10GE or FC1200 clients. The Nx10G FPGA is a single chip multi-lane solution for multi-protocol transponder/mapper (e.g. 10x10GE to OTN, 20xFC1200 to OTN, 40x10GE to OTN, etc). Each lane is individually configurable through an easy to use Software Application Programming Interface (API) or customizable software driver.
AES-GCM encryption is optional add-on feature to further enhance the power of spider SOC.
If the SOC is put on FPGA, the transponder/mapper is fully customizable and tailored to individual s need.
The N x 10G Transponder solution provides a complete solution for up to N lanes of multiple client data transport to a SDH/SONET/Ethernet WIS or OTN network. Each lane is individually, dynamically re-configurable through a software API. On the client side, the transponder connects directly to a XFP or SFP+ or XAUI interface. The client signal is transcoded and mapped depending on the desired application.
Existing 10G transponder/mapper solutions offer 1 to 4 lanes per chip. Our FPGA solution can offer much higher lane (port) density per chip, typically 4, 8, 10, 12, 16, 20, 32, 40 or higher (depending on FPGAs). As a result of higher port density, better power efficiency and cost effectiveness can be obtained.
- Line Interface
- OTU2+G.709 GFEC
- STM-64c/OC-192c/Ethernet WIS
- Client Interface
- 10G Ethernet
- FC1200 Fiber Channel (FC)
- 10GBASE-R or 10GBASE-X (XAUI)
- Direct connection to XFP with XFI or to SFP+ with SFI or XAUI
- Ethernet MAC + RS Link (Optional)
- Ethernet frame delineation adhering to 802.3
- Statistics gathering
- Required for GFP mapping applications
- GFP-F Encapsulation and Delineation (Optional)
- Compliant to G.7041
- Provides optional IDLE insertion and removal
- OTN Mapper +GFEC
- Maps BMP mapped or GFP encapsulated payload to OPU2e/OPU2
- OPU/ODU/OTU Overhead generation including alarms. OH fields programmed through software registers or via an OH insertion interface.
- Optional G.709 GFEC generation (with external processor)
- OTN De-mapper +GFEC
- ODU/OTU frame alignment with programmable FAS
- ODU/OTU overhead processing including detection of faults
- OTU/ODU/OPU overhead monitoring. Capture of registers for software processing of slow changing fields or option to send to an OH extraction interface for processing by an external device.
- Optional G.709 GFEC processing (with external processor)
- Processor Interface
- Simple request-acknowledge register access to 16/32-bit registers for device configuration and statistic collection.
- Fully customizable FPGA load
- Application Programming Interface
- Complete API for ease of use for configuration, error processing and monitoring.