10GHz to 15GHz Broadband Wireless Microwave Receiver Front-End on GF 130nm
SRAM on EF 28 Embedded Flash Platform in TSMC 28nm ESF3
High Density SRAM contains HD 6T-bitcell for high density purpose; while High Performance SRAM contains HC 6T-bitcell for high performance requirement. All these two compilers take M31 2nd generation of low power SRAM architecture with Source Bias Enable (SBE) which supplies the alternative option during the retention mode for 70% leakage-saving, comparing to that of 28HPC+ SRAM. Furthermore, the new feature provides the Asynchronous Write-Through (AWT) function for fast data retrieval and access with flexible margin optimization for the trade-off between performance and memory capacity. The new next-generation memory design adopts the high-sigma design methodology to optimize the variety of memory capacity demands.
M31 completes the development of memory compilers on tsmc 28ESF3, which is widely used in high-speed data processing, graphics computing, power management, and handheld mobile communication design. The ULL SRAM bit cells provide the outperformance leakage and these compilers contain two devices, VT options, “SVT”&”SVT+uHVT”, to provide the attractive performance for speed and power requirements. It provides chip design more competitive characteristic for the embedded flash products.
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High Density IP
- High performance, flexible, extendible 32 bit microcontroller core featuring excellent code density
- SMIC 0.18um High Density Standard Cell Library
- SMIC 0.15um High Density Standard Cell Library
- SMIC 0.25um High Density Standard Cell Library
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- High Density Two Port Reg File Compiler - SMIC 28 nm 28PSe