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SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since the SSTL_15/18 normally operates with its own isolated power domain (1.5V/1.8V), a “rail-splitter” support cell (SPP_RS_005_15V) is included to allow the designer to easily break the lines that should not connect to the rest of the padring, while allowing VDD and VSS to be continuous within the padring.
Features
- Full DDR3 capability - 800MHz (1600 Mbps)
- Full DDR2 capability
- Low Power driving standard DDR3 memories
- 2.5V FETs
- Full complement of cells to build padring (20)
- Full ODT Capability - dynamic 6-Bit PVT calibration (external reference resistor)
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
View SSTL_15_18 IO Pad Set full description to...
- see the entire SSTL_15_18 IO Pad Set datasheet
- get in contact with SSTL_15_18 IO Pad Set Supplier
ESD IP
- ESD solution set for LV & advanced processes
- High ESD analog IO library
- Analog I/O Pads with and without ESD Protection
- TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- High-voltage solutions in baseline TSMC & GlobalFoundries technologies
- ESD solution set for HV/BCD processes