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SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both single-ended and differential signaling. This single pad set supports both the DDR2 and DDR3 signaling standards.
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SSTL IP
- SSTL_15 / SSTL_18 Combo I/O Pad Set
- SSTL_ I/O Pad Set
- SSTL_15 / SSTL_18 Combo I/O Pad Set
- DDRI/II/III SSTL/HSTL combo interface with RTT (rectangle) - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF
- DDRI/II/III SSTL/HSTL combo interface with RTT (square) - TSMC 80nm GC (CLN80GC)
- DDRI/II/III SSTL/HSTL combo interface without RTT (rectangle) - TSMC 90nm LP (CLN90LP)