The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully compatible with a Standard FIFO interface and they may be mixed and matched. A “Stall” may be generated by gating the POP and ORDY signals to arrest the normal flow of data down the pipeline and allows any given stage to take multiple cycles when necessary. In doing so the IRDY signal is removed in the following cycle and the data that was to replace the data in the primary register is saved into the secondary register. When the “Stall” is removed the the secondary register contents are copied to the primary register and the IRDY is re-asserted for the next clock edge.
- Fully Synthesizable RTL - Verilog
- Static Timing Analysis compatible
- Double Register for synchronous pipeline
- Configurable width
- Standard FIFO handshake interface
- verilog RTL and Testbench
- Fully Synchronous pipelines