The AMBA® AHB interface is ideal for system that requires Multi-master, Multi- transaction, and back-to-back transactions. AHB supports the efficient communication between processors, on-chip memories and off-chip external memory interfaces with low-power peripheral devices. This AHB bus interface can be customized to support up-to 16 Masters and 16 Slaves. At any point of time on the bus arbitrator selects the Master selected to initiate the transaction AHB support single Read and Write as well as Burst transactions.
- Completely Configurable registers and memories
- Configurable bus width up to 64/128 bits
- single clock edge operation
- Questa VIP verified
- Burst transfer
- An AMBA AHB interface can be generated using available configuration tools. Designers can use IDesignSpec which helps them to write executable specification and generate the outputs. IDesignSpec captures simple as well as complex registers, signals, interrupts, sequences and other artifacts that constitute the hardware/software interface. It can then generate not only ARM based bus peripherals for buses like AXI, AHB, APB etc., but also the C/C++ API for firmware and software development teams. The RTL code generated for the peripherals can be in SytemVerilog, Verilog or VHDL. In addition, code for verification is generated for UVM verification environment and formal assertions. IDesignSpec also imports other forms of executable specification such as SystemRDL, IP-XACT, CSV, RALF and any XML. An important aspect of the development, namely, the hardware/software interface is now handled by this tool, engineers are free to focus on the “real” system development, resulting in lower number of resources required.
- Verified & Synthesizable Verilog/VHDL Source Code with SV UVM Test bench
- Formal Assertions for protocol verification
- Detailed Documentation – (AHB peripheral Documentation)
- Configurable register IP generator – using IDesignSpec
- Technical support
- DV services (at additional cost)
- ARM based SoC designs , SW/HW interface design & Integration