The xc-SDDIA core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used either for display or further processing such as H.264 video compression. The core implements a state-of-the-art motion-adaptive algorithm that blends the pixels of the two fields as a function of its spatial and temporal characteristics resulting in very high pixel quality even with difficult motion scenes.
- Deinterlaces standard 4:2:2 interlaced video streams into 4:2:0 raster streams.
- Advanced pixel-based, motion-adaptive algorithm produces very high image quality.
- Directly connects to 8-bit, 4:2:2 interlaced video source
- Video format support includes either BT.656 or raw input with HSYNC,VSYNC timing.
- Extremely low input-output latency of two video lines.
- Variable output frame rate starting with twice the input field rate (50 fps)
- Configurable input truncator supports D1, 4CIF and VGA sizes.
- Very low core frequency equal to the output pixel rate (typically 27Mhz).
- Simple external memory interface suitable with a wide variety of memory controllers
- Fully synchronous, pipelined design
- Bit-accurate executable model
- Comprehensive testbench and documentation
- Reference design available
- Core netlist or RTL source code
- Synthesis constraints
- Comprehensive testbench with input video test file library, regression test scripts
- Windows/Linux bit-accurate model
- Developer's guide, specifications and system integration guide
- Complete reference design (optional)