400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Stream Buffer Controller
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Block Diagram of the Stream Buffer Controller IP Core
Stream Buffer Controller IP
- Stream Buffer Controller
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect