The Xelic SONET/SDH Transport Processor Core (XCS3F) performs transport overhead processing, aligns incoming SONET/SDH frames and provides overhead interpretation with error detection and performance monitoring. The XCS3F contains independent transmit and receive processors with dedicated external ports for overhead insertion and extraction. Incoming/outgoing data is transferred at an STS-3/STM-1 rate using an 8-bit data bus operating at 19.44Mb/s.
The XCS3F Transmit Processor inserts transport overhead, calculates and inserts B1/B2 parity (with corruption capability), automatically generates line RDI, and scrambles (with corruption capability) SONET/SDH frames. A programmable trace buffer is implemented for 1 byte, 16 byte or 64 byte trace message insertion. Diagnostics support includes optional corruption of inserted parity, corruption of scrambling, framing corruption, and programmable generation of line AIS, and line RDI conditions.
The XCS3F Receive Processor contains a configurable frame alignment unit with programmable options for OOF and LOF algorithm state transitions. Incoming frames are descrambled (optional) and aligned for transport overhead processing. Transport overhead information is extracted to internal register locations and dedicated section DCC, line DCC, section orderwire, line orderwire, and transport overhead external ports. Transport overhead interpreters are implemented to detect and report various conditions which include LOS, LOF, LOA, OOF, B1 error, SD, SF, B2 error, AIS-L, and RDI-L errors with optional maskable interrupt generation provided. LOS detection is available through either an incoming signal or an internal programmable LOS detection algorithm. Section Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM) and trace identifier unstable (TIU) conditions. Line AIS is inserted through programmable internal register control. Diagnostics support includes optional corruption of calculated parity, corruption of descrambling, and Line AIS generation.
Performance counters (configurable for bit or block count type) are provided for the accumulation of detected OOF, B1 parity, B2 parity and REI errors for incoming SONET/SDH frames. B2 parity errors are accumulated with programmable threshold capability for signal degrade (SD) and signal fail (SF) detection. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCS3F provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.