The Xelic SONET/SDH Concatenated STS-48c/STM-16 Framer Core (XCS48C) aligns incoming SONET/SDH frames and provides transport overhead processing, path overhead processing and pointer processing for contiguous concatenated SONET/SDH payloads types. The XCS48C contains independent Transport Processor and Concatenated Path Processor modules with dedicated external ports for overhead insertion and extraction. Incoming/outgoing data is transferred at an STS-48c/STM- 16 rate using a 32-bit data bus operating at 77.76Mb/s.
The XCS48C Transmit Transport Processor inserts transport overhead, calculates and inserts B1/B2 parity (with corruption capability), automatically generates line RDI, and scrambles (with corruption capability) SONET/SDH frames. A programmable trace buffer is implemented for 1 byte, 16 byte or 64 byte trace message insertion. Diagnostics support includes optional corruption of inserted parity, corruption of scrambling, framing corruption, and programmable generation of line AIS, and line RDI conditions.
The XCS48C Transmit Concatenated Path Processor inserts high order path overhead, calculates and inserts B3 parity (with corruption capability), and automatically generates path RDI. A programmable trace buffer is implemented for 16 byte or 64 byte trace message insertion. Normal and bypass modes of operation are supported. In normal mode, incoming payload information is requested for insertion into the outgoing SONET/SDH SPE frame cavity. A fixed outgoing pointer is provided with an option to program any legal value (0 to 782) for generated frames. POH byte information can be inserted through internal register control or from an external overhead port.
The XCS48C Receive Transport Processor contains a configurable frame alignment unit with programmable options for OOF and LOF algorithm state transitions. Incoming frames are descrambled (optional) and aligned for transport overhead processing. Transport overhead information is extracted to internal register locations and dedicated section DCC, line DCC, section orderwire, line orderwire, and transport overhead external ports. Transport overhead interpreters are implemented to detect and report various error conditions which include LOS, LOF, LOA, OOF, B1, SD, SF, B2, AIS-L, and RDI-L with optional maskable interrupt generation provided. LOS detection is available through an incoming signal or an internal programmable LOS detection algorithm. Section Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM-L) and trace identifier unstable (TIU-L) conditions. Line AIS is inserted through programmable internal register control. Diagnostics support includes optional corruption of calculated parity, corruption of descrambling, and Line AIS generation.
The XCS48CPP Receive Concatenated Path Processor extracts high order path overhead to both internal registers and an external path overhead port. Path Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM) and trace identifier unstable (TIU) conditions. Path AIS is optionally inserted and maskable interrupts are generated for detected Path Trace Identifier Unstable (TIU-P), Path Trace Identifier Mismatch (TIM-P), Signal Degrade (SD), Signal Fail (SF), Path Signal Label Unstable, and/or Path Unequipped (UNEQ-P) error conditions. An incoming path RDI interpreter reports detected RDI-P, ERDI-P, and path RDI unstable errors. Incoming Synchronous Payload Envelope (SPE) information is extracted and passed to the external system side interface with valid data indication provided through a dedicated output.
Performance counters (configurable for bit or block count type) are provided for the accumulation of detected OOF, B1 parity, B2 parity B3 parity, REI-L errors, REI-P errors, pointer increment or decrement events, and pointer NDF occurrences for incoming SONET/SDH frames. B2 and B3 parity errors are accumulated with programmable threshold capability for signal degrade (SD) and signal fail (SF) detection. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCS48C provides a variety of facility and terminal loopback modes of operation for Transport Processor and Concatenated Path Processor functions using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.