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STS48/STM16 Pointer/Path Processing to concatenated STS48c level
The Xelic SONET/SDH Concatenated High Order Path Processor Core (XCS48CPP) performs path overhead processing and pointer processing for contiguous concatenated SONET/SDH payloads types. The XCS48CPP contains independent transmit and receive processors with dedicated external path overhead ports and a generic register interface to provide flexible insertion and extraction capability. Incoming/outgoing data is transferred at an STS-48c/STM-16 rate using a 32-bit data bus operating at 77.76Mb/s.
The XCS48CPP Transmit Processor inserts path overhead, calculates and inserts B3 parity (with corruption capability), automatically generates path RDI, and supports Tandem Connection source or sink configurations with programmable Incoming Signal Fail (TC-ISF) detection. A programmable trace buffer is implemented for 16 byte or 64 byte trace message insertion. An integrated pointer interpreter provides programmable state machine operation which includes options for 8 of 10 pointer objective and single AIS state transitions. Incoming Synchronous Payload Envelope (SPE) information is extracted and passed through an internal FIFO for insertion into outgoing SONET/SDH frames. A pointer generator is provided for applications with different clocks (nearly same timing) at the line and system side interfaces (plesiochronous boundaries). Diagnostics support includes fixed payload data insertion, AIS-P or VC-AIS generation, and the ability to manipulate pointers (pointer increment, decrement, NDF capability) in outgoing SONET/SDH frames. A flexible system side interface is provided for synchronized frame start or telecom bus signaling.
The XCS48CPP Receive Processor extracts path overhead to both internal registers and an external path overhead port. Path Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM) and trace identifier unstable (TIU) conditions. Tandem Connection source or sink configurations with programmable Incoming Signal Fail (TC-ISF) detection is provided. Path AIS is optionally inserted and maskable interrupts are generated for detected Path Trace Identifier Unstable (TIU-P), Path Trace Identifier Mismatch (TIM-P), Signal Degrade (SD), Signal Fail (SF), Path Signal Label Unstable, Path Unequipped (UNEQ-P), and/or Loss of Multiframe (LOM) error conditions. An incoming path RDI interpreter reports detected RDI-P, ERDI-P, and path RDI unstable errors. Incoming Synchronous Payload Envelope (SPE) information is extracted for each path and passed through an internal FIFO for insertion into outgoing SONET/SDH frames. A pointer generator is provided for applications with different clocks (nearly same timing) at the line and system side interfaces (plesiochronous boundaries). Diagnostics support includes fixed payload data insertion, AIS-P or VC-AIS generation, and the ability to manipulate pointers (pointer increment, decrement, NDF capability) in outgoing SONET/SDH frames. Synchronous frame start and telecom bus signaling is generated at the system side interface to identify various SONET/SDH frame byte positions.
Performance counters (configurable for bit or block count type) are provided for the accumulation of detected Tandem Connection IEC errors, B3 parity errors, Path REI errors, pointer increment or decrement events, and pointer NDF occurrences for interpreted or generated pointer processing of SONET/SDH frames. B3 parity errors are accumulated with programmable threshold capability for signal degrade (SD) and signal fail (SF) detection. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCS48CPP provides facility and terminal loopback modes of operation for Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
The XCS48CPP Transmit Processor inserts path overhead, calculates and inserts B3 parity (with corruption capability), automatically generates path RDI, and supports Tandem Connection source or sink configurations with programmable Incoming Signal Fail (TC-ISF) detection. A programmable trace buffer is implemented for 16 byte or 64 byte trace message insertion. An integrated pointer interpreter provides programmable state machine operation which includes options for 8 of 10 pointer objective and single AIS state transitions. Incoming Synchronous Payload Envelope (SPE) information is extracted and passed through an internal FIFO for insertion into outgoing SONET/SDH frames. A pointer generator is provided for applications with different clocks (nearly same timing) at the line and system side interfaces (plesiochronous boundaries). Diagnostics support includes fixed payload data insertion, AIS-P or VC-AIS generation, and the ability to manipulate pointers (pointer increment, decrement, NDF capability) in outgoing SONET/SDH frames. A flexible system side interface is provided for synchronized frame start or telecom bus signaling.
The XCS48CPP Receive Processor extracts path overhead to both internal registers and an external path overhead port. Path Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM) and trace identifier unstable (TIU) conditions. Tandem Connection source or sink configurations with programmable Incoming Signal Fail (TC-ISF) detection is provided. Path AIS is optionally inserted and maskable interrupts are generated for detected Path Trace Identifier Unstable (TIU-P), Path Trace Identifier Mismatch (TIM-P), Signal Degrade (SD), Signal Fail (SF), Path Signal Label Unstable, Path Unequipped (UNEQ-P), and/or Loss of Multiframe (LOM) error conditions. An incoming path RDI interpreter reports detected RDI-P, ERDI-P, and path RDI unstable errors. Incoming Synchronous Payload Envelope (SPE) information is extracted for each path and passed through an internal FIFO for insertion into outgoing SONET/SDH frames. A pointer generator is provided for applications with different clocks (nearly same timing) at the line and system side interfaces (plesiochronous boundaries). Diagnostics support includes fixed payload data insertion, AIS-P or VC-AIS generation, and the ability to manipulate pointers (pointer increment, decrement, NDF capability) in outgoing SONET/SDH frames. Synchronous frame start and telecom bus signaling is generated at the system side interface to identify various SONET/SDH frame byte positions.
Performance counters (configurable for bit or block count type) are provided for the accumulation of detected Tandem Connection IEC errors, B3 parity errors, Path REI errors, pointer increment or decrement events, and pointer NDF occurrences for interpreted or generated pointer processing of SONET/SDH frames. B3 parity errors are accumulated with programmable threshold capability for signal degrade (SD) and signal fail (SF) detection. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCS48CPP provides facility and terminal loopback modes of operation for Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
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