The CL12612IP Receiver converts the 3-channnel sub-LVDS serial data streams back to parallel 24bits of LVCMOS. The CL12612IP Receiver is an ideal means to solve EMI and cable size problems associated with wide, high speed CMOS interface.
- Input Clock: 80MHz to 340MHz
- Input Data Rate: 160Mbps~680Mbps
- Output Clock: 20MHz~85MHz shift clock support
- Low power single 1.8V or 2.8/3.3V (Option: 1.0/1.2/1.8/2.5V Logic/Level Shifter)
- Narrow bus reduces cable size
- Power down mode
- sub-LVDS DDR format
- This specification is Sony 12-bit CIS Parallel Interface specification.
- This IP is used in Mobile-Phone and DSC products.
- This IP is used in ISP products.
- Our sub-LVDS technology is very small consumption current.
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP used this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file