The MIPS P5600 processor IP core is the first member of the Warrior generation of MIPS CPU cores from Imagination Technologies. It delivers industry leading 32-bit performance with class-leading low power characteristics, and in a silicon footprint up to 30% smaller than comparable alternatives in the industry. The P5600 CPU core was designed for the performance and features required for tomorrow’s mainstream connected consumer electronics including smartphones, tablets, connected TVs and set-top boxes. However, the rich and broad feature set extends applicability into a variety of networking applications, from residential gateways to network appliances and microservers.
The MIPS P5600 CPU is based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture, supporting up to six cores in a single cluster with high performance cache coherency. Complementing this raw horsepower, this core is the first in the MIPS CPU lineup to include 128-bit integer and floating point SIMD processing, hardware virtualization, and physical and virtual addressing capability enhancements.
The MIPS P5600 processor IP core delivers top line performance while being the most efficient CPU core in its class, making it ideal for both mobile and digital home applications in the rapidly growing connected consumer electronics market.
It builds upon the existing proAptiv family microarchitecture, adding 128-bit SIMD, hardware virtualization with hardware table walk, 40-bit eXtended Physical Addressing (XPA), and substantial gains in performance on system-oriented software workloads. The P5600 CPU also exceeds 5 CoreMark/MHz per core, a score significantly higher than any published score for licensable IP cores in the industry, and achieves 3.5 DMIPS/MHz, matching or exceeding other high end IP cores as well.
The P5600 processor delivers this performance in a much smaller silicon footprint than leading IP core alternatives, achieving these results in up to 30% smaller silicon area , given a common process geometry, similar configurations and synthesis techniques used. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage against competing silicon.