Agnisys, Inc., the pioneer and industry leader in Golden Executable Specification Solutions™, is a provider of Electronic Design Automation (EDA) software and methodology services to help you create, verify, validate, integrate, package, and reuse Intellectual Property (IP). Aimed at solving complex frontend design, verification, and validation problems, its certified IDesignSpec™ Solution Suite leverages a golden executable specification to capture and centralize registers, sequences, and connectivity for IP and System-on-a-Chip (SoC) projects. Intuitive user interfaces and standards-based workflows dramatically reduce risk by eliminating development errors while significantly increasing productivity and efficiency through the automatic generation of collateral for your entire product development team.
Agnisys leverages industry standards so that register transfer level (RTL) designs are generated in Verilog, VHDL, and SystemC, and include interfaces for bus standards such as APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, I2C, SPI, and Wishbone. Generated standard IP blocks include AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART.
Founded in 2007, Agnisys is headquartered in Boston, Massachusetts, with R&D centers in the United States and India.
Our Products Agnisys solutions are used by today’s market makers across a wide range of market segments to create, verify, validate, integrate, package, and reuse IP.
With Agnisys specification automation solutions, many specifications can be written in executable formats from which design, programming, verification, validation, and documentation files are automatically generated. Each time the specification changes, all files are automatically regenerated with all the changes incorporated, replacing tedious manual effort while keeping all your teams in sync at all times.
The Agnisys IDesignSpec Solution Suite further streamlines the development process by leveraging industry standards. RTL designs are generated in Verilog, VHDL, and SystemC, and include interfaces for bus standards such as APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, I2C, SPI, and Wishbone. Generated standard IP blocks include AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART.
Verification and validation environments and tests are generated in SystemVerilog compliant with the Universal Verification Methodology (UVM). Generated C/C++ code is standard compliant. Documentation is generated in HTML, PDF, Markdown, and DITA formats.
Other file formats supported include SystemRDL, IP-XACT, YAML, JSON, RALF, and CSV. Customization scripts can use standard Tcl, Python, and Velocity. In addition, the Agnisys IDesignSpec Solution Suite has been certified as meeting the ISO 26262 and IEC 61508 safety standards, thereby enabling semiconductor designers to create products that satisfy these functional safety standards for automotives and road vehicles as well as safety critical manufacturing.
The Agnisys IDesignSpec Solution Suite offers your product teams a closely linked set of solutions that can be shared across all teams to maximize efficiency and support fully automated flows:
- IDesignSpec™ GDI – Graphical Interface and Interactive Generator: It provides a complete solution for executable hierarchical specification of your memories, register sets, registers, and register fields in an IP or SoC. You can choose from a variety of input formats and import existing descriptions in standard formats such as SystemRDL, IP-XACT, JSON, RALF, YAML, XML, and CSV files.
- IDS-Batch™ CLI – Command Line Generator: It provides a complete solution for executable hierarchical specification of the memories, register sets, registers, and register fields in your IP or SoC. You can choose from a variety of input formats and import existing descriptions in standard formats such as SystemRDL, IP-XACT, and CSV files. You can also specify the registers and memories using Agnisys-supplied templates and Add-Ins for Microsoft Word, Microsoft Excel, OpenOffice Calc or using the specialized graphical interface of IDesignSpec GDI.
- IDS-Verify™ – Verification Tests and Environment: It is used for automatic register test, custom register-based sequences, and testbenches in simulation as well as formal verification of registers. It enables you to describe the custom configuration, programming, and test sequences of your design and automatically generate sequences ready to use during your RTL simulation. From a single sequence specification, IDS-Verify generates UVM sequences for verification and associated documentation. You specify the sequences using a rich language and command feature set that includes loop, branch, wait, call, switch, and macro.
- IDS-Validate™ – Validation Tests and Environment: The register verification capabilities of IDS-Verify are extended to your pre-silicon and post-silicon validation by IDS-Validate. It automatically generates both UVM and C/C++ sequences, including specified custom sequences, that exhaustively test your memories and registers. IDS-Validate also extends beyond registers and memories to generate verification environments and user-defined functional tests to verify the functional behavior of your custom design blocks.
- IDS-Integrate™ – Smart SoC Assembly: It is used to apply specification automation to SoC-level assembly and interconnection. IDS-Integrate provides a flexible and customizable environment to meet the design requirements for your complete chip. It not only interconnects blocks, but it also generates RTL components such as bus multiplexers, aggregators, bridges (AHB to APB, AXI to APB, and AXI4-Full to AHB-Full), and other “plumbing” components as needed. Additionally, IDS-Integrate fully comprehends the register RTL designs generated by IDesignSpec GDI and the IP blocks generated by IDS-IPGen. It can also handle any third-party IP block with an IP-XACT description, including your custom design blocks.
- IDS-IPGen™ – Configurable Standard and Custom IP: It automatically generates IP blocks from specifications that are highly configurable and customizable. IDS-IPGen supports a wide variety of standard IP blocks as well as the specification of finite state machines (FSMs), data paths, signals, and other parts of your custom IP blocks. For both standard and custom blocks, it generates RTL models, UVM verification models, and verification tests that provide high functional and code coverage right out-of-the-box.
Our Vision To accelerate your front-end SoC, FPGA, and IP development to help ensure your project success.
Our Mission Agnisys aims to automate design, verification, validation, and documentation files from golden executable specifications.
Industry Partnership & Association We partner with leading EDA companies, including Siemens EDA, Cadence, and Aldec, to ensure a smooth working flow between our tools and theirs, for our common customers. We are a member of Accellera, active on a number of working groups, contributing to the development of industry standards.
Management & Advisory Board Anupam Bakshi
Founder and CEO
Anupam Bakshi is the founder and CEO at Agnisys. He has more than two decades of experience implementing a wide range of products and services in the High-tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel Corporation, Blackstone Consulting Group, Cadence Design Systems, and Gateway Design Automation. Anupam has earned a HighTech MBA from Northeastern University, Massachusetts, a Masters in Computer Engineering, also from Northeastern University, and a Masters in Science (Electronics) from Delhi University.
Don Schuler
Advisory Board Member
Don Schuler is a CAE/EDA veteran with over 30 years of experience in the development, use, and support of computer tools for hardware design. Most recently he was Director of Engineering Services and Manager of Tools and Verification at Avid Technology. At Avid he led the verification and back-end work on several ASICs and FPGAs at the heart of Avid’s Oscar winning Film Composer. Previously he led the System Design and Logic Simulation teams at CAE startup Viewlogic. Before that he was Productivity Manager at Apollo/HP where he built an extensive CAE environment using mainly commercially available tools that included tools for ASIC, PCBs, and mechanical design. Initially Don spent 10 years at GTE Laboratories developing simulation, test generation, and ASIC layout tools. He is co-inventor of Concurrent Fault Simulation, holds a patent on simulation techniques, and has published several papers including two Best Paper Awards on design methodologies. Another paper was selected for the Design Automation Conference 25th Anniversary Proceedings. During his time in CAE Don has evaluated dozens of CAE tools and was an early adopter of several new and innovative tools.
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