Agnisys, Inc. IP Catalog
About Agnisys, Inc.
Agnisys builds innovative products that solve complex design and verification issues. It has R&D centers in India and USA manned by a highly talented & creative team. Agnisys has established itself as leading Electronic Design Automation (EDA) supplier with more than 500 users worldwide. Its products use patented technology and provide intuitive user interfaces with high-end technology underneath. As a result, Agnisys’ products are now de-facto standards in many industry verticals e.g. Defense and Avionics. Agnisys, Inc. was formed in 2007 in Massachusetts USA, by industry leaders having more than two decades of experience in EDA and Semiconductors with an aim to bring in automation through continuous innovation, saving time while raising the standards of quality, in pursuit of excellence.
IDesignSpec™ is Agnisys’ flagship, award winning product that enables an IP, chip or system designers to create the register map specification for their digital system once and automatically generate all of the required outputs from it. It helps create peripherals for AMBA buses such as AXI, AHB, APB and others such as OCP-IP, MIPI, I2C, SPI etc.
A wide range of outputs such as UVM, OVM, RALF, SystemC, SystemRDL, IP-XACT are generated along with user defined outputs created using Tcl or XSLT scripts. IDesignSpec’s patented technology helps in raising the productivity & design quality, while reducing the time required for each task.
Automatic Register Verification (ARV™) is an add-on to IDesignSpec™ that expands an already powerful register specification solution with its capability to automate the register verification process for SoCs, IP and FPGA. ARV saves the semiconductor teams’ time and improves quality by enabling complete code coverage for design registers that are the key integration point for semiconductor design, IP, software and interfaces.
ISepenceSpec helps design teams to generate unified test and programming sequences in UVM and Firmware from a single specifications. ISequenceSpec uses the register information by importing the standard formats like IP-XACT, SystemRDL, and XML. A user can define the test sequences in a simple editor, and then generate the unified test sequences from verification to validation. The test generated are UVM sequences for simulation and firmware sequences for HW/SW co-simulation and post silicon validation like start-up sequence, read-write operation shutdown sequence, low power mode sequence etc.
DVinsight™-Pro is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.DV Engineers can create ‘correct-by-construction’ DV code as DVinsight-Pro is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards. It helps in shortening the learning curve of new DV engineers while accelerating error-free code development by expert DV developers.
IDS NextGen is a multi-platform product which helps a user to create SoC specification at an enterprise level. It handles individual IP to sub-system to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, System RDL. IDS NextGen generates design and verification code for not just registers but sequences in one integrated environment. It reduces the verification time by generating the entire UVM SV and SystemC output sequences.
To be the enabler of fastest path to chip realization from specification.
By creating high quality, specification centric products for semiconductor industry realize the fastest path to chip from specification.
Industry Partnership & Association
We partner with leading EDA companies like Mentor Graphics, Synopsys, Cadence, Aldec, to name a few, to ensure a smooth working flow between our tools & that of the vendor’s, for our common customers
Management & Advisory Board
Founder and CEO
Anupam is the founder and CEO at Agnisys. He has more than two decades of experience implementing a wide range of products and services in the High Tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel Corporation, Blackstone Consulting Group, Cadence Design Systems and Gateway Design Automation. Anupam has earned a HighTech MBA from Northeastern University, Massachusetts, a Masters in Computer Engineering also from Northeastern University and a Masters in Science (Electronics) from Delhi University.
Advisory Board Member
A CAE/EDA veteran with over 30 years of experience in the development, use and support of computer tools for hardware design. Most recently he was Director of Engineering Services and Manager of Tools and Verification at Avid Technology. At Avid he led the verification and back-end work on several ASICs and FPGAs at the heart of the Avid’s Oscar winning Film Composer. Previously he led the System Design and Logic Simulation teams at CAE startup Viewlogic. Before that he was Productivity Manager at Apollo/HP where he built an extensive CAE environment using mainly commercially available tools that included tools for ASIC, PCBs and mechanical design. Initially Don spent 10 years at GTE Laboratories developing simulation, test generation and ASIC layout tools. He is co-inventor of Concurrent Fault Simulation, holds a patent on simulation techniques, and has published several papers including two Best Paper Awards on design methodologies. Another paper was selected for the Design Automation Conference 25th Anniversary Proceedings. During his time in CAE Don has evaluated dozens CAE tools and was an early adopter of several new and innovative tools.
Agnisys, Inc. IP Listing
2 Product(s) Listed