56G Ethernet PHY IP in 12FFC
The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the DesignWare Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.
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Video Demo of the 56G Ethernet PHY IP in 12FFC
This OFC 2019 video demo shows Synopsys’ 56G Ethernet PHY IP running across multiple 400G interconnects. The IP is capable of operating across backplanes and optical, copper cables in QSFP-DD, OSFP, and SFP-DD form factors, meeting the IEEE 802.3cd standard. Synopsys’ PHY enables designers to meet their reach and performance requirements of their next-generation 400G hyperscale data center SoCs
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