The V6800 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular 8-bit MC6800 microprocessor. The V6800 is intended to be used in system-on-a-chip applications constructed using gate-arrays or standard cells. It should be especially interesting to designers who currently use MC6800s in embedded control applications and want to integrate its functionality with other designs/peripherals/etc. onto a single chip (ASIC).
The V6800 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock.
The V6800 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.