Syntill8's Four-Wire slave IP for use with the Mentor M8051W and M8051EW

Features

• Implementation of a four-wire synchronous full-duplex slave interface, compatible with the Motorola SPI bus
• Supports various message protocols using byte granularity data
• Programmable clock phase and clock and select polarity
• Supports any four-wire clock rate, independent of microcontroller clock rate
• Integral transmit and receive data FIFOs minimise the processor overhead required to service the link
• Supports both interrupt-driven and polled transfers
• Optional clock prescaler minimises power consumption while active
• Rests in power saving mode when the interface is not enabled
• Slave select wake up feature can be used to cold start a M8051W and M8051EW microcontroller, in addition to interrupt driven wake ups
• Binds tightly to M8051W and M8051EW external interrupt and SFR buses with no additional glue logic required

Benefits

• The M4WIS is designed to bind tightly to an M8051W or M8051EW SFR bus. Data, control and status information are exchanged with the host microcontroller using memory-mapped 8-bit words. A single interrupt signal is used to indicate that a matching address has been received, that data buffers require service or that an exception has been detected. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA design

Deliverables

• VHDL '93 and Verilog 2001 RTL source code
• VHDL and Verilog functional demonstration testbench
• Demonstration assembler code
• Simulation scripts for Modelsim and Cadence
• Synopsys synthesis compile scripts and SDC timing constraint files
• Example Mentor DFT and ATPG scripts
• Example netlist implementation with SDF files
• Detailed product specification and a user guide containing implementation notes

Block Diagram of the Syntill8's Four-Wire slave IP for use with the Mentor M8051W and M8051EW

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