tail-biting Viterbi decoder for WiMAX - silicon proven

Features

• K=7 (64 states) G0=171(octal), G1=133(octal).
• Rate ½. Other rates can be supplied by external puncturing.
• Decoding of 1 or 2 bits per clock algorithms.
• Parameterizable input soft width.
• Parameterizable input traceback length.
• On the fly configurable trace back length, to support low latency.
• Supports tail biting.
• Throughput > 155 Mbit/sec on FPGA.
• Area/Power efficient architecture utilizing RAM for trace back storage
• All-synchronous design using a single clock, except for global asynchronous reset.
• Available as verilog source code or as netlist.

Deliverables

• Verilog source code or verilog EDIF netlist.
• Verilog testing environment
• Bit-exact Matlab model
• Documentation

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