The CoreTBItoEPCS IP Core is a bridge that appears between the Ten-Bit Interface (TBI) and External PCS (EPCS). The Core supports Ten-Bit interface Rx/Tx data bus on TBI side and 20-bit Rx/Tx data bus on EPCS side. This block receive TBI data (with double data rate) and transmit on EPCS bus and vice-versa. CoreTBItoEPCS includes user testbench for verification.
- TBI and EPCS clocks are asynchronous to each other
- TBI clock frequency = 62.5 MHz and EPCS clock frequency = 125 MHz
- Data on the TBI (TCGF/RCGF) bus comes with double data rate
- TBI data width is 10 bits
- EPCS data width is 20 bits but only 10 bits are used, depending on the UPPER_EPCS parameter/generic
- This bridge accepts data from the TBI only after PHY is ready (EPCS_READY), assuming that the TBI will not send data until the PHY is ready