The AC2380 TDM over Packet device implements Circuit Emulation Services Interworking Functions (CES IWF) for a fully channelized OC 12 or STM 4 capacity. Each of the 336 DS1 or 252 E1 channels embedded on the line interface are processed individually to provide a high-density Gateway between TDM over SONET/SDH and TDM over packet.
The device integrates all functions for TDM transport gateway applications in wireless backhaul systems: SONET/SDH line interfaces with 1+1 APS protection, VT 1.5/VC 12 mappers, E1/DS1 framers, TDMoP IWF, and packet header processing.
The AC2380 implements the SAToP and CESoPSN modes defined by IETF, MEF, MFA and ITU. These support transport of transparent DS1/E1 channels, or provide bandwidth efficient nx64 fractional channels.
Each TDM channel can be configured independently for adaptive, differential or retiming clock recovery mode, and each channel may operate at a different clock rate.
The integrated DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The device supports Ethernet, VLAN, IP and MPLS PWE3 packet headers, and a dual Gigabit Ethernet interface.
The device is ideally prepared for new protocols or standards evolution due to its FPGA based design.
Evaluation systems are available for system level testing.
- TDM over Packet CES IWF for 336 DS1s, 252 E1s
- SAToP or CESoPSN transport mode selectable per channel (RFC4553 and RFC5086)
- Configurable amount of TDM data per packet
- Clock recovery mode selectable per channel: adaptive, differential or retiming mode
- RTP header for differential clock (RFC3550)
- Jitter and wander compliant to MEF18, ITU-T G.8261 and G.823 / G.824 for traffic interfaces
- Configurable jitter buffer size
- Extensive set of CES fault and performance monitoring points
- The integrated SONET/SDH framer/mapper supports SOH/POH, pointer processors, and VT 1.5/VC 12 mappers
- DS1/E1 framers provide alarm, fault and performance monitoring, and support for loopbacks and PRBS maintenance functionality
- Integrated packet header processor for MAC addresses, VLAN tags, IP and MPLS PWE3 headers
- 1 OC-12/STM-4 or 4 OC-3/STM-1 line interfaces
- Dual GbE SerDes or interface to external PHY
- Clock: 19.44 MHz
- DDR2 DRAM for jitter buffer
- 16-bit CPU interface
- High density TDM over packet equipment
- Aggregation or gateway card on MSPP, Carrier Ethernet Switch or IP/MPLS Router
- RNC or BSC controller network interface card
- CMTS cable head-end
- AMC I/O cards for ATCA and MicroTCA
Block Diagram of the TDM over Packet Gateway device IP Core