TDM over Packet Gateway device
The device integrates all functions for TDM transport gateway applications in wireless backhaul systems: SONET/SDH line interface with 1+1 APS protection, VT-1.5/VC-12 mappers, E1/DS1 framers, TDMoP IWF, and packet header processing.
The AC2560 implements the SAToP and CESoPSN modes defined by IETF, MEF, MFA and ITU. These support transport of transparent DS1/E1 channels, or provide bandwidth efficient nx64 fractional channels.
Each TDM channel can be configured independently for adaptive, differential or retiming clock recovery mode, and each channel may operate at a different clock rate.
The integrated DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The device supports Ethernet, VLAN, IP and MPLS PWE3 packet headers, and a dual Gigabit Ethernet interface.
The device is ideally prepared for new protocols or standards evolution due to its FPGA based design.
Evaluation systems are available for system level testing.
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Block Diagram of the TDM over Packet Gateway device IP Core
