A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an exclusively digital interface and includes a power down function to reduce standby current. The temperature sensor can be instanced multiple times in a single chip. Tight thermal control of device activity is essential for performance optimization, power efficiency and long-term reliability. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.