MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
Ternary-CAM/Binary-CAM, supports process G/LV
View Ternary-CAM/Binary-CAM, supports process G/LV full description to...
- see the entire Ternary-CAM/Binary-CAM, supports process G/LV datasheet
- get in contact with Ternary-CAM/Binary-CAM, supports process G/LV Supplier
memory compiler IP
- Ultra High-Speed Cache Memory Compiler
- TSMC CLN12FFC Ternary Content Addressable Memory Compiler
- TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
- TSMC CLN7FF Pre-search and Pipeline Ternary Content Addressable Memory Compiler
- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k