Low jitter, ultra-low power (<950uW) ring-oscillator-based PLL-2.4GHz
TFT/LCD/MIPI Display Controller and Composition Engine
The core is designed to lift the workload off the Graphics Processing Unit (GPU) or the host processor (CPU), in GPU-less systems, and minimize the memory bandwidth. Multiple layers can be clipped, positioned and composed on the final display by overlaying video, subtitles, graphics, cursor or application windows, with or without transparency.
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Block Diagram of the TFT/LCD/MIPI Display Controller and Composition Engine
Video Demo of the TFT/LCD/MIPI Display Controller and Composition Engine
This demo demonstrates the Nema|dc Multilayer Display Controller- Composition Engine.
The demo runs on the Xilinx Zynq ZC706 development board driving a display with resolution of 1024x600 pixels . It features a single colored background, four framebuffer layers and a mouse pointer. Each layer incorporates a scaler (up/down with bilinear filtering) and a programmable blender. The CPU is responsible only for grabbing the mouse events and calculating the layers' position. All animations, rotating/blending/scaling/filtering operations and scene composition are done entirely by the NEMA|dc IP module without any CPU or GPU utilization