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ARC VPX5 high-performance, 512-bit VLIW / SIMD DSP IP for high-end computation applications
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TFT/LCD/MIPI Display Controller and Composition Engine
NEMA®|dc is a powerful display controller which contains several smart tools and functionalities to compose multiple graphics and video layers by improving image quality and contributing significantly to the reduction of the SoC power consumption. NEMA®|dc supports powerful composition features, a wide range of display interfaces, and advanced proprietary frame-buffer compression technology.
The core is designed to lift the workload off the Graphics Processing Unit (GPU) or the host processor (CPU), in GPU-less systems, and minimize the memory bandwidth. Multiple layers can be clipped, positioned and composed on the final display by overlaying video, subtitles, graphics, cursor or application windows, with or without transparency.
The core is designed to lift the workload off the Graphics Processing Unit (GPU) or the host processor (CPU), in GPU-less systems, and minimize the memory bandwidth. Multiple layers can be clipped, positioned and composed on the final display by overlaying video, subtitles, graphics, cursor or application windows, with or without transparency.
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Block Diagram of the TFT/LCD/MIPI Display Controller and Composition Engine
Video Demo of the TFT/LCD/MIPI Display Controller and Composition Engine
This demo demonstrates the Nema|dc Multilayer Display Controller- Composition Engine.
The demo runs on the Xilinx Zynq ZC706 development board driving a display with resolution of 1024x600 pixels . It features a single colored background, four framebuffer layers and a mouse pointer. Each layer incorporates a scaler (up/down with bilinear filtering) and a programmable blender. The CPU is responsible only for grabbing the mouse events and calculating the layers' position. All animations, rotating/blending/scaling/filtering operations and scene composition are done entirely by the NEMA|dc IP module without any CPU or GPU utilization