This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Storage Memory is implemented by External Single Port Memory without any drop in Bandwidth on any port.
It has option to select CDC mythology and CDC Clock ratio to make it more stable operating at different set of freq.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Uses External OnChip Single Port Memory for Storage of Data
- 1. Fully stable operation.
- 2. Non-2**n depth supported.
- 3. Dip-In and Data Available support.
- 4. CDC method and CDC clock ratio selectable.
- 5. Good memory packing density help user to implement large FIFOs
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
- Internal IP Component Block
- can be used inside any IP/SOC.