MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
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