TIMER is used to generate delays, signals with timing characteristics and measure the time between signal edges, compatible with standard protocol of TIMER specification. Through its TIMER compatibility, it provides a simple interface to a wide range of low-cost devices. TIMER IIP is proven in FPGA environment.The host interface of the TIMER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
- Compliant with JEDEC TS5111, TS5110 specifications.
- Full TS5 Master Controller Functionality.
- I2C with maximum speed up to 1 MHz
- I3C with maximum speed up to 12.5 MHz
- Supports I3C Master/ Slave address arbitration.
- Supports all command codes specified in specification
- Supports Packet error check
- Supports Parity error check
- Supports device read address pointer mode.
- Support HCI mode of command control
- Support Non-HCI mode of command control
- In-Band Interrupt support
- Bus reset support
- Supports all error handling as per specs
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The TIMER interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.