The DUART is one of the tiniest UART IP Cores available on the market.
The DUART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The DμART has processor-interrupt system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the communications link.
The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.
- Majority Voting Logic
- Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
- In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data.
- Independently controlled transmit, receive, line status, and data set interrupts.
- 16 bit programmable baud generator
- False start bit detection
- Line break generation and detection. Internal diagnostic capabilities:
- ○ Loop-back controls for communications link fault isolation
- ○ Overrun, framing error detection
- Full prioritized interrupt system controls
- Technology independent HDL Source Code
- Fully synthesizable static design with no internal tri-state buffers
- Single-Site license option – dedicated to small and middle sized companies, which run their business in one place.
- Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches.
- In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use.
- Source code:
- ○ VHDL Source Code or/ and
- ○ VERILOG Source Code or/ and
- ○ Encrypted, or plain text EDIF
- VHDL & VERILOG test bench environment
- ○ Active-HDL automatic simulation macros
- ○ Model Sim automatic simulation macros
- ○ Tests with reference responses
- Technical documentation
- ○ Installation notes
- ○ HDL core specification
- ○ Datasheet
- Synthesis scripts
- Example application
- Technical support
- ○ IP Core implementation support
- ○ 3 months maintenancence
Block Diagram of the Tiny UART IP Core