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TSMC 4/5/6/7/12/16/28nm eFPGA Tiles
The EFLX®4K Tile is an embeddable standalone FPGA IP core, with 3 versions, that communicates with the rest of your SoC using input and output pins on the edges. For more logic capacity we can abut tiles to make larger arrays (up to ~8x8) with any combination of tile versions.
The three versions of the EFLX tile are described below – they are all the same dimensions so they can be intermixed in arrays. The DSP MAC is a 22x22 multiplier with 48- bit accumulator arranged in 4 row of 10 pipelined MACs.
The EFLX 4K tiles have numerous input and output pins. Each input or output pin has a bypassable flip flop. When multiple cores are concatenated into EFLX arrays, the pins along the abutting edges are disabled or are used for controlling embedded RAM blocks (BRAMs).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each Core has an internal power grid which can be connected to the customer’s digital SoC power grid. The Core also has configuration inputs on the West side and configuration inputs on the South side to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connection points. The configuration bits can be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications.
The three versions of the EFLX tile are described below – they are all the same dimensions so they can be intermixed in arrays. The DSP MAC is a 22x22 multiplier with 48- bit accumulator arranged in 4 row of 10 pipelined MACs.
The EFLX 4K tiles have numerous input and output pins. Each input or output pin has a bypassable flip flop. When multiple cores are concatenated into EFLX arrays, the pins along the abutting edges are disabled or are used for controlling embedded RAM blocks (BRAMs).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each Core has an internal power grid which can be connected to the customer’s digital SoC power grid. The Core also has configuration inputs on the West side and configuration inputs on the South side to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connection points. The configuration bits can be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications.
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