IGMTLSV04A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM). It is developed with TSMC 12nm 0.8V/1.8V CMOS LOGIC FinFET Compact Process. Different combinations of words and bits could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMTLSV04A compiler is capable of providing suitable synchronous TCAM instances models within minutes. It is capable of automatically generating data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold times and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.