The IGAPLLV03A is a General purpose Phase Lock Loop (PLL), without external components and is designed to provide stable and accurate clock. The IGAPLLV03A incorporate several frequency dividers for different application.
The VCO frequencies range from 1.6GHz to 3.6GHz by divider setting and reference clock from 10MHz to 225MHz. The feed-back clock input pin can support the clock de-skew application.
A power-down mode is available to shut down the power of PLL circuit. Bypass and power down modes are both available.
- TSMC 16nm CMOS Logic FIN FET PLUS LL
- 1.8V analog supply operation and 0.8V digital supply operation
- 10 to 225 MHz input clock
- Input/output clock de-skew
- Power-down capability
- Bypass mode
- Lock detection function
- Chip area: 240um*270um