The IGALVDT01A IO receiver converts the 24-channel SubLVDS (Sub-Low Voltage Differential Signaling) or SLVS (Scalable Low-Voltage Signaling) data streams to the 24-lane 0.9V CMOS data output; individually. The 20 data channels consist of 16 data lanes in the main sensor and 4 data lanes in the sub sensor. Each sensor consists of the individual clock input. The SubLVDS/SLVS data channel receives the data rate up to 1.1Gpbs with the clock rate up to 550MHz. A 100Ω on-chip termination is built on each receiver input and the power down control signal is used for the power saving. An individual signal detection circuit is built in each SubLVDS/SLVS IO receiver to guarantee a stable receiver output and avoid the noise disturbance. The SubLVDS/SLVS receiver is designed for the low-power application using TSMC 28nm HPM 0.9V/1.8V process.
- * TSMC 28nm HPM 0.9V/1.8V process, 1P8M 5X2Z.
- * 1.8V analog supply operation and 0.9V digital supply operation
- * 550 MHz differential clock input
- * Individual input signal detection
- * 100Ω on-chip input termination
- * Individual data and clock lane control for the main and sub sensors
- * Power-down capability