IGAPLLS04B is a general purpose deskew Phase Locked Loop (PLL) without external component. It is designed to provide a stable and accurate reference clock for digital circuitries. Broadly, this PLL circuit optimizes the phase jitter performance with the limited current consumption and the robust VCO architecture.
The PLL incorporates several frequency dividers to generate various output frequencies for different application. The feedback clock input pin can support the clock de-skew feature. A power down mode is available to shut down the power of the PLL circuit. A bypass mode is also provided to bypass the output clock of PLL to the external reference clock.
- TSMC 40nm low power process
- 3.3V or 2.5V analog supply operation and 1.1V digital supply operation
- 25 to 170 MHz reference input clock
- Input/output clock de-skew
- Power-down capability
- Bypass mode
- Lock detection function