IGADDRS06A supports LPDDR3 and DDR3/4 SDRAM. The PHY IP is designed to be used with LPDDR3 and DDR3/4 Controller IP to provide a complete DDR IP solution. A DFI interface is provided by this PHY IP to connect to the memory controller IP.
The PHY architecture’s performance scales from (LP)DDR3-800 Mbps to (LP)DDR3-1866. All DDR PHY macro signals from and to the controller are synchronous to the memory controller clock (MC_CLK). The PHY-Controller interface can be clocked at 1:2 of the DDR CK clock naturally. For example, for DDR3-800 Mbps system, users shall be running memory controller MC clock at 200 MHz (1:2 ratio). The PHY’s DQ data path width scales in 8-bit increments with additional data modules inside the DDR PHY macro. The LPDDR3 and DDR3/4 PHY IP optionally supports multiple (up to 2) ranks so that the CS#[1:0], ODT[1:0], and CKE[1:0] signals from the controller are synchronized by the PHY
IGADDRS06A LPDDR3 and DDR3/4 PHY IPs include one hard macro and one RTL module (for miscellaneous logic blocks of PHY IP). The hard macro includes command address module, data module, IO pads, PLL and DLL components required for DDR PHY function. The RTL module is the miscellaneous logic block (MLB RTL block) provided to work with the DDR PHY hard macro. The MLB RTL module includes functions such as training logic, JTAG controller interface for PHY DFT registers, loop back BIST logic, ODT control logic and PHY resistors calibration logic. The PHY evaluation mode is provided through MLB logic without the help of controller to complete the training sequences such as IO PVT calibration, CA training, read gate training, read data EYE training and write data EYE training which are required to guarantee DDR PHY IP functions. MLB training procedure is default enable in initial sequence to set DDR PHY by hardware as described in Section 2.3. This DDR PHY MLB RTL module shall be integrated in SOC by users to work with DDR PHY hard macro correctly.
IGADDRS06A LPDDR3 and DDR3/4 PHY IP architecture also supports a memory controller evaluation mode training interface for read Gate training and read data EYE training features which are required to guarantee DDR PHY IP functions. Both gate training and read data eye training interface signals are described in technical manual and users are recommended to connect the training interface to user-defined registers so that users are able to set DDR PHY through these user-defined register by software.
- (LP)DDR3 and DDR4 SDRAM PHY
- (LP)DDR3-800 to 1866 Mbps for 40LP nm process node
- Complete DDR PHY solution including I/O, PLL, and DLL
- DQ width scalable in 8-bit increments
- All LPDDR3 and DDR3/4 PHY IP signals from/to Controller are synchronous to MC clock
- Support DFI 3.1/2.1 interface
- Support 2:1 DDR CK to memory controller clock ratio
- Support CA training, write leveling, gate training, write, read eye training, vref training.
- Support up to 4 ranks
- Support IO PVT(process, voltage and temperature) automatic calibration function
- Support optional multiple CK/CK# differential clock pairs for better signal integrity
- Support optional AUX power domain for power saving function
- Support CA swapping
- Support DQ swapping