The “IGAPLLS12A” is low jitter general purposes de-skew Phase Locked Loop (PLL) without external component. Broadly, this PLL circuit optimizes the phase jitter performance with the limited current consumption and the robust VCO architecture.
The PLL incorporates several frequency dividers to generate various output frequencies and provides VCO 8phase output clock signals for different application. A power down mode is available to shut down the power of the PLL circuit. A bypass mode is also provided to bypass the output clock of PLL to the external reference clock.
- TSMC 40nm low power process
- 2.5V /3.3V analog supply operation and 1.1V digital supply operation
- 10 to 800 MHz input clock range
- 10 to 100 MHz reference clock range
- VCO 8phase output clock signals
- Low phase jitter
- Power-down capability
- Bypass mode
- De-skew mode
- Lock detection function