The IGALVDS04B FPD-link receiver converts the five LVDS (Low Voltage Differential Signaling) data streams back into parallel 35bits of 1.1V CMOS data. The data throughput rate of LVDS signals is up to 3.15Gpbs. The Receiver’s outputs are falling edge strobe (Figure 3 4, Figure 3 5). The IGALVDS04B requires only five off-chip line-termination resistors for the differential inputs. An active-low power down input can be used to inhibit the clock and shut off the LVDS receivers for lower power consumption.
The FPD-link LVDS receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be pulled to a HIGH state. This is the case if not all data channels are required in the application. Leave the extra channel’s inputs open or connect inputs to AVDD. This minimizes power dissipation and locks the unused channels outputs into a stable known (HIGH) state. If a clock signal is present, data outputs will all be HIGH; if the clock input is also floating with terminator, data outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output.
The LVDS Receiver is designed in TSMC 40nm CMOS logic low power Salicide 1.1V/2.5V process.
- TSMC 40nm CMOS logic low power salicide 1.1V/2.5V process.
- 3.3V/2.5V analog supply operation and 1.1V digital supply operation
- 25 to 100 MHz shift clock support (dual channel)
- Support spread spectrum clock tracking (+/-5%@30KHz, +/-3%@300KHz)
- Falling-edge clock triggered outputs
- PLL lock detection output
- Support floating and terminated input fail-safe
- Power-down capability